This position is to work with a global leader company in the design and development of advanced semiconductors, responsible for architectures and platforms that form the core of some of the most innovative devices on the market. Its silicon engineering drives solutions that deliver high performance, energy efficiency, and intelligent integration, complemented by a key role in advancing modern telecommunications through next-generation wireless connectivity technologies. Its solutions are integrated into billions of devices worldwide, offering an ideal professional environment for talent seeking technological impact, innovation, and growth within a global context.

The position requires Synthesis or/and Place and Route experience and CAD development skills to define and develop implementation tools and methodologies for PPA, Quality and shortening design cycle time, in close collaboration with Implementation and Physical Design teams.

This role’s responsibilities will include.

• Improving the SoC Synthesis, Formal Verification, Place and Route methodologies for diverse Mobile, Compute, AI, IoT chips.
• Enabling new features from EDA tools or/and internal tools for PPA, turn-around time or enabling new advanced process nodes.
• Support design teams on CAD solutions, analyze their requests, and address their requests through ticket queues.
• Interfacing with EDA vendors to enable production-ready tool sets that satisfy project’s requirement.
• Setting up, augmenting, and maintaining a regression of complex Synthesis, P&R designs.
• Innovating on tool/flow techniques for area reduction, dynamic power reduction and turn-around time, leading to participation to patents.

Preferred Qualifications.

• Masters degree or PhD in Computer Engineering, Electrical Engineering, or related field.
• 2-6 years of experience in VLSI CAD, preferably Synthesis, Floorplan, Place and Route on SoCs at either top-level or block-level.
• 2-6 years of experience with scripting tools and programming languages: Python and TCL preferred.

Principal Duties and Responsibilities.

• Participate to the Synthesis, Place and Route and Formal verification flows enablement for foundry advanced process nodes.
• Participate to the tuning of design recipes to address specific objectives such as area, turn-around time on various subsystems such as Modem, GPU, CPU, DDR, Camera, Video, NSP.
• Interface and drive EDA vendor Application Engineers on the resolution of block convergence problems faced by the design teams.
• Participate to the specification of new CAD solutions addressing the PPA requirements of the design teams.
• Deep dive on Implementation issues, such as cell legalization issues, congestion hotspots, always-on feedthrough management, clock H-tree and CTS etc.
• Participate along with talented AI team to R&D initiatives driving differentiation in terms of die area reduction and turn-around time.