#QP

#VLSI

#QP

#VLSI

Digital Design Engineer

Job Description

Company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age and this is where you come in.

Digital Design Engineer for Mixed-Signals IPs, ASICs and Chipsets used in power solutions. IPs include telemetry ADCs, 100W+ charging (Quick Charge 5.0), 5G power (mmW, envelope tracking, high performance low noise oscillators etc…) and high efficiency power management (DC-DC charge pumps, bucks and linear regulators).

Work includes partnering with international teams in all stages of development from system definition to high-volume (100M+) OEM launches.

Successful applicants will be responsible for participating in, or leading, the design of state-of-the-art Mixed-Signals ASICs in advanced digital deep sub-micron CMOS processes for multi-function mobile platforms.

Responsibilities will include all, or some, of the following:

• Micro-architecture of chipset, chip and IP-level designs (designs include firmware, RTL and analog hard macros)
• Negotiating and executing System specification and requirements
• Actively involved in all aspects of the front-end design from Architecture definition/RTL development/Simulation/Synthesis/DFT Insertion/Static Timing closure and closely work with the Place and Route function.
• Document ASIC development, hold detailed design reviews with cross-functional teams, generate and maintain design schedules.

Preferred Qualifications

• MS+2 Years ASIC design, verification, or related work experience

• Applicants should have sound digital design principles with exposure to Front-end Digital design tools – HDL, RTL Linting, CDC, Synthesis, BIST/SCAN insertion, STA.
• Strong communication and organizational skills
• Strong process-oriented mindset.

Minimum Qualifications

• Bachelor's degree in Science, Engineering, or related field.
• 3+ years ASIC design, verification, or related work experience

Job Description

We are looking for talented and ambitious individuals to join the TECHIP team. The candidate should have strong IP modeling, Char tool know-how and hands-on experience and automation skills. Hands-on experience in EDA tool automation, data analysis and visualization & large-scale software automation enablement. Excellent understanding of statistical Liberty timing, power model and Front-end Verilog views and tools. Silicon reliability modeling, validation with multiple foundries & EDA house is a plus.

Minimum Requirements:

• Strong Std cell / Memory circuit knowledge & IP characterization, Design Kit delivery background.
• Strong logical and problem-solving skills with excellent analytical and debugging skills
• Strong Software programming skills in Python or Perl in UNIX/Linux computing platform
• Highly motivated, excellent team spirit and good communication skills.

• Ability to work in multi-site project teams, third party vendors to drive cutting edge tools, flows in QCOM environment for characterization flow and sign-off methodologies

Preferred Qualifications:

• In depth technical knowledge of CMOS, FinFET logic and transistor, basic of digital circuit design optimization 
• Familiar with industry standard Design kit (DK) views, Liberty formats for foundation IPs (advanced modeling formats CCS, LVF) , statistical variation models & worked on development of the same.
• Familiarity with front end pre-silicon design flow, RTL design/coding, logic design, Verilog/ System Verilog, RTL design verification, System Verilog Assertion (SVA), Design for Test, BIST modeling experience.
• Expertise in scripting in Python (data-analytics), Perl & experience in developing large scale automation from scratch.
• Experience in STA, physical design is a plus.
• Experience of spice simulation models, design rules verification procedures (like DRC/LVS/ERC) is a plus.

The ideal candidate would also have experience with industry standard chip design tools and design flows for Static Timing Analysis, Spice / Fast spice simulation, Synthesis, DFT, Power Analysis

Education Qualifications

• Required: Bachelors, Electrical Engineering or Computer Engineering or Computer Science
• Preferred: Master's, Electrical Engineering or Computer Engineering or Computer Science

Work Experiences:

0 - 3 years Library characterization or Custom circuit design or CAD flow development or VLSI related work experience.

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