Identificador oferta:
57377
Fecha de Publicación:
02-03-2026
Resumen
The candidate will work with best-in-class methodologies, tools, and technology to design innovative SOC products at the block/IP-level and at system-level in 5nm, 4 nm,m and beyond (process technologies).
- You will be working with the physical design team (and other teams) on timing closure, CAD teams, IP teams, and Design Technology Teams for flow scripts/tools development and validation.
- Responsible for Spice simulations (Hspice/Primesim/Finesim/AFS/Spectre) for PVT corners validation and STA vsSpicee correlation. Timing package validation across advanced process technologies using PT/PT-SI and Tempus.
- You will facilitate and drive STA methodology for Qualcomm using PT-SI, Tempus, and best-in-class timing ECO tools. Work on timing sign-off specification for different projects and support timing sign-off for complex SoCs. Hands-on contribution for STA timing sign-off.
- A timing Engineer should be able to understand all kinds of intricate timing paths (digital, analog, mixed signal), timing constraints, and provide solutions if required. Good understanding of RTL to GDS digital flow. Knowledge of DC/DCT/DCG/FC/Genus/Oasis, ICC2/FusionCompiler/Innovus/Aprisa, RedHawk/SeaHawk/Voltus is a plus.
- You should have good execution knowledge.
- Your contribution should improvethe timing convergence process across the company, design PPA, yield, and support new advanced process technologies bring-up from PDK to VLSI design production.
- You should have good programming skillsin Python, Perl, TCL, Unix shell, and C/C++.
- ML modeling experience is a plus.
3041378 ASIC Timing and Technology Engineer, Staff
As a Timing Engineer, you will play a vital role in Timing analysis targeting the Mobile, Compute, Automotive, and IOT markets.
- The candidate will work with best-in-class methodologies, tools,s and technology to design innovative SOC products at the block/IP-level and at system-level in 5nm, 4nm, and beyond (process technologies).
- You will be working withthe physical design team (and other teams) on timing closure, CAD teams, IP teams, and Design Technology Teams for flow scripts/tools development and validation.
- Responsible for Spice simulations (Hspice/Finesim/PrimeSim/AFS/Spectre) for PVT corners validation and STA vs Spice correlation. Timing package validation across advanced process technologies using PT/PT-SI and Tempus.
- You will facilitate and drive STA methodology for Qualcomm using PT-SI, Tempus, andbest-in-classs timing ECO tools. Work on timing sign-off specification for different projects and support timing sign-off for complex SoCs. Hands-on contribution for STA timing sign-off.
- A timing Engineer should be able to understand all kinds of intricate timing paths (digital, analog, mixed signal), timing constraints,s and provide solutions if required. Good understanding of RTL to GDS digital flow. Knowledge of DC/DCT/DCG/FC/Genus/Oasis, ICC2/FusionCompiler/Innovus/Aprisa, RedHawk/SeaHawk/Voltus is a plus.
- You should have good execution knowledge.
- Your contribution should improve the timing convergence process across the company, design PPA, yield, and support new advanced process technologies bring-up from PDK to VLSI design production.
- You should have good programming skillsin Python, Perl, TCL, Unix shell, and C/C++.
- ML modeling experience is a plus.