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Semiconductor, semiconductores, procesador, procesadores, silicio, telecomunicaciones, ingeniero, ingenieros, ASIC, diseño VLSI, microelectrónica, electrónica, circuitos integrados, tecnología semiconductora, nodos avanzados, diseño de chips, fabricación de semiconductores, industria de semiconductores, talento semiconductor, empleos semiconductores, Static timing analysis, STA, timing convergence, corner definition, nodos tecnológicos, leading edge, semiconductor technologies, timing signoff, full chip timing closure, tape-out, post-silicon analysis, ASIC Timing analysis, timing corners, timing closure, PPA improvement, timing bottleneck, Mobile, Compute, Automotive, IOT, physical design, CAD, IP teams, Design Technology Teams, Primetime, Tempus, timing ECO tools, RTL to GDS, mixed-signal SoCs, low-power techniques, clock gating, power gating, multi-voltage designs, Python, Perl, TCL, Unix shell, data processing, timing convergence, team player, comunicación, multitasking, IP design, timing sign off.
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Mechanical design, server rack platforms, outdoor cabinet enclosures, consumer mobile device test platforms, test platforms, product core team, industrial design team, mechanical engineering design team, product mechanical design, detail design, thermal simulations, tooling, fabrication, product testing, manufacturing transition, Geo, USA, India, China, EU, mechanical engineering packaged design, 3D solid modelling, Proe, Creo, PCBs, packaged design, plastic injection molded parts, Die Cast, Sheet metal parts, 3d printed, CNC machined parts, wire harness design, cable harness design, platform electrical interconnects, stack up tolerance analysis, Antenna design, RF, Thermal, ID constraint requirements, form factor designs, heat transfer, electromechanical enclosures, thermal mitigation, electronics packaging, fabrication methods, CNC, Sheetmetal, Plastic Injection molding, Die Casting, 3D printing, electro-mechanical assemblies, top-down solid modelling, 3D database design, mechanical engineering, analysis fundamentals, circuit board assembly layout, connector placement, board design, EMN file creation, EMP file creation, electrical PCB CAD design, 3D CAD tools, CREO, test fixture design, assembly platform fixture design, PDM systems, Agile, BOM, project management, forced-air thermal dissipation, convection thermal dissipation, consumer mobile, test rack, outdoor infrastructure, electro-mechanical platforms, RF teams, antenna teams, baseband teams, EMI regulatory teams, thermal teams, product management teams, system-level mechanical enclosure concepts, component specification, form factor, design tradeoffs, multi-disciplinary team collaboration, analytical simulations, electrical hardware teams, mfg engineering, product requirements, schedule, program budgets, design fundamentals, fabrication fundamentals, procurement fundamentals, CNC parts, injection molded parts, 3d printed parts, die-cast parts, stamped metal parts, project goals, project peers, mfg engineering, program leadership, e-mail communication, virtual meetings, onsite meetings, instant messaging, status reports, presentation slides, product development processes, schedule execution, multitasking, aggressive schedules, dynamic design environment, design reviews, test fixture design integration, assembly, test, English communication, troubleshoot, assembly issues, part quality issues, BSME, Mechanical Engineering.
#jrg
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System test, correlation, cellular, wireless peripherals, 4G, 5G, SLT, system test solutions, Customer Quality, silicon industry, IC design review, IC hardware testing, software development, system engineering, customer applications, silicon bring-up, post-silicon validation, integrated system performance, HW/SW interaction, Digital device performance, RF device performance, operating conditions, voltage, process, thermal, production screens, system level issues, volume ramp, chipset architecture, test board designs, NPI test solutions, production test solutions, system level testers, 5G product roadmap, testing automation tools, test outputs, proactive, fast-paced environment, dynamic environment, individual contributor, deliverables, quality work, silicon validation, System test, SW test, bench test, HW-SW interactions, mobile devices, microprocessor industry, specifications analysis, HW schematics, data sheets, silicon validation test cases, Android Architecture, Android Boot process, Kernel, Core BSP, Android Performance, computer architecture, operating systems, Android, Windows, Linux, Processors, Graphics, Memory, Thermal performance, Power performance, SOCs, debugging, triaging, Android debugging tools, JTAG Lauterbach, Trace32, Perforce, GIT, Source Control SW, measurement equipment, Oscilloscopes, Power Supplies, Wireless Network Simulators, Embedded SW development, FPGA programming, C#, .NET Framework, C, C++, Perl, Python, SW development, Android platform, Windows platform, Linux platform, RF specifications analysis, test plans, test execution, RF measurements, 3GPP specifications, Bench characterization, new instrument evaluations, production solution development, Electrical Engineering, Computer Science, Computer Engineering, Tijuana.
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Digital communications, networks, 3GPP specifications, test plans, system performance, 5G, LTE-A, Wi-Fi systems, automation, test analysis, system performance issues, vendors, clients, network performance, technical results, Electrical Engineering, RTP, TCP, UDP, IP protocols, optimization tools, QXDM, TEMS, Actix, programación, C, C++, Python, MATLAB, LFT, life insurance, savings fund, medical expense insurance, grocery voucher, tecnologías inalámbricas, pruebas, análisis, rendimiento, colaboración, resultados técnicos, protocolos de red, herramientas de optimización, habilidades de programación, beneficios laborales, ingeniero de comunicaciones, especificaciones 3GPP, planes de prueba, problemas de rendimiento, evaluación de red, presentación de resultados, ingeniería eléctrica, inglés fluido.
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Wireless Systems Engineer, integración, optimización, wireless systems, rendimiento, debugging, field tests, OTA, nuevas funcionalidades, equipment suppliers, interoperabilidad, system performance, diseño, capacity estimation, network management, nuevas tecnologías, performance studies, laboratorio, technical documents, white papers, nuevos estándares, Electrical Engineering, 5G-Advanced, 5G, Wi-Fi, LTE-Advanced, data services, protocolos, RTP, TCP, UDP, IP, planning tools, optimization tools, Atoll, iBwave, QXDM, TEMS, Ethereal, Actix, Agilent, R&S, Spirent, PCtel, programación, C, C++, Perl, Python, MATLAB, ML libraries, PyTorch, Keras, Scikit, cellular technologies, operadores, infraestructura, pruebas de campo, proveedores, capacidad de red, documentos técnicos, estudios de rendimiento, tecnologías celulares, servicios de datos, herramientas de planificación, herramientas de optimización, habilidades de programación, librerías ML, inglés conversacional.
#ITSEP24
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#SQ
#Shantal
Emulation Platforms, FPGA Prototyping, Veloce, Palladium, Emulation tools, Synthesis, Place and Route, Constraints, Clocking, System Debug, Waveform generation, Content Debug, SoC Functionality, CPU Core, DSP Core, Multimedia, IO, Peripherals, DDR, Modem, Bus Protocols, synthesizable models, emulation deployment, SoC design, debug skills, Tools, Technology, Flows, pre-silicon prototyping, bus transactors, jtag transactors, memory, LPDDR3, LPDDR4, PCDDR, System Verilog, UVM, JTAG, kernel debuggers, ARM CPU, SoC architectures, ADI, AMBA, ARM v8, digital circuits, scripting, Python, TCL, Computer Engineering, Computer Science, Electrical Engineering, Electronics Engineering, Verilog, Design Verification, ASIC Design.
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#JRG
Intelligent, high potential, learning, DDR interface, JEDEC spec, bus level, transactions, regression testing, PVT testing, Emulation Build Validation, C code, code flow, code manipulation, test iteration, Post-Si test execution, data review, logic design, hardware debug, low level software issues, hardware issues, debug tools, JTAG, kernel debuggers, post-silicon enabling, bring-up, logic analyzer, DDR bus, Tijuana, relocation packages.
#ITSEP24
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#SWDEV
System validation framework, IP validation framework, bare-metal, light-weight-rtos, SoC validation, SoC architecture, test plan, system validation content, low power use cases, HW bugs, root cause, Design teams, Software teams, IP validation team, cross functional teams, silicon debug hooks, power, performance, coverage, KPI metrics, Embedded SW architecture, C, C++, Assembly, C language, low level programming, hardware-software boundary, assembly language, ARMv8, ARMv9, x86, RISC-V CPU architecture, Interrupt handling, Cache coherency, IO Coherency, SoC architecture, Multicore, Multiprocessor, SMP, heterogenous cores, Operating systems, RTOS, Linux kernel internals, multithreading, scheduling policies, locking mechanism, Virtual memory, MMU, paging, memory management, weakly ordered memory model, pipelining, memory systems, memory barriers, software build toolchains, compilers, Makefiles, linker, scatter files, GCC, CLANG, RVDS, LLVM, code optimization, linker issues, JTAG interfaces, debugging HW, scripting languages, Python, shell scripting, Software engineering best practices, code reviews, static analysis tools, code quality, clean code, SoC architecture, interconnects, power management, emulation, pre-Si, silicon enablement, silicon validation, Board Bring-up, FPGA, emulation platforms, SOC designs, build automation, Jenkins, automated build pipelines, Regression testing, regression test suites, software quality, stability, Source code management, Perforce, Git, SVN, branching, merging, merge conflicts.
#jrg
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#VLSI
#SWDEV
SOC validation, digital hardware, SoC silicon, architects, designers, verification engineers, software engineers, customers, SOC Infrastructure, NoC validation, Performance validation, pre-silicon emulation, post-silicon validation, digital design fundamentals, on-chip interconnects, SOC bus architecture, SOC bus performance, SOC Bandwidth, QoS, Latency, Throughput analysis, Interconnect architectures, NoCs, AXI, AHB, FIFO designs, performance validation plans, Performance-Power trade-offs, low power modes, dynamic clock scaling, dynamic voltage scaling, Interrupt architecture, Debug architecture, JTAG debuggers, state dump scripts, Performance monitor architecture, CPU concepts, DDR concepts, Multimedia, GPU, Peripheral, Memory hierarchy, caches, coherency, consistency, memory types, memory attributes, synchronization, semaphores, full-system concurrency, MTE, MPAM, embedded systems, C, C++, Python, assembly languages, drivers, test content, low level software issues, hardware issues, debug tools, JTAG, kernel debuggers, structured program development, performance metrics, testing methodologies, performance validation tests, test results analysis, performance reports, cross-functional teams, performance issues resolution, performance testing tools, frameworks, ASIC design, ASIC verification.