If you have expertise in Timing area and are excited by driving leading edge semiconductor technologies those make differences on this world, this is the opportunity for you.

In this highly visible role, the candidate is expected to coordinate with 100+ engineers, work across multiple design teams in USA and beyond USA, work inside and with outside company/vendor, juggle various tech node issues concurrently.

Role skills:

• You should have good programming skills Python, Perl, TCL, Unix shell, C/C++.
• Experience in various STA tools
• Timing signoff margin development
• Timing sign off Corner development
• Full chip timing closure
• Tape-out
• Post-silicon analysis is a plus
• ML modeling experience is a plus

As a Timing and Technology engineer, you will be responsible for all aspects of timing including, defining corners, helping construct and/or modify flows, PPA improvement, timing bottleneck analysis and timing closure.

The candidate will work with best-in-class methodologies, tools and technology to design innovative SOC products at the block/IP-level and at system-level in 5nm, 4nm and beyond (process technologies).

Responsibilities

• You will be working with physical design team (and other teams) on timing closure, CAD teams, IP teams and Design Technology Teams for flow scripts/tools development and validation.
• Responsible for Spice simulations (Hspice/Primesim/Finesim/AFS/Spectre) for PVT corners validation and STA vs spice correlation. Timing package validation across advanced process technologies using PT/PT-SI and Tempus.
• You will facilitate and drive STA methodology using PT-SI, Tempus and best in class timing ECO tools. Work on timing sign off specification for different projects and support timing sign off for complex SOC’s. Hands-on contribution for STA timing sign off.
• A timing Engineer should be able to understand all kinds of intricate timing paths (digital, analog, mixed signal), timing constraints and provide solutions if required. Good understanding of RTL to GDS digital flow. Knowledge of DC/DCT/DCG/FC/Genus/Oasis, ICC2/Fusion Compiler/Innovus/Aprisa, RedHawk/SeaHawk/Voltus is a plus.
• You should have good execution knowledge.
• Your contribution should improve timing convergence process across the company, design PPA, yield and support new advanced process technologies bring-up from pdk to vlsi design production.

To work on site at Santa Fe, Tijuana. We provide relocation bonus if you live out of Tijuana.