Descripción

This position is to work with a global leader company in the design and development of advanced semiconductors, responsible for architectures and platforms that form the core of some of the most innovative devices on the market. Its silicon engineering drives solutions that deliver high performance, energy efficiency, and intelligent integration, complemented by a key role in advancing modern telecommunications through next-generation wireless connectivity technologies. Its solutions are integrated into billions of devices worldwide, offering an ideal professional environment for talent seeking technological impact, innovation, and growth within a global context.

Join our growing international team as a Standard Cell Layout Designer—no prior industry experience required. We’re looking for candidates with strong academic foundations, excellent attention to detail, and a desire to learn cutting-edge technologies.

As a Standard Cell Layout Designer, you will work with highly standardized layout blocks—the “Lego pieces” of digital CMOS circuit libraries. Your main responsibility is to assemble and optimize these blocks according to strict design rules so that every cell fits together perfectly, without gaps or mismatches.

This team differs from custom analog layout groups: the focus is on systematic, rule-based work, precision, and layout consistency across large-scale libraries used in advanced semiconductor technologies.

You will work closely with global engineering teams, follow detailed specifications, and grow your skills in layout methodologies, CAD tools, scripting, and advanced semiconductor nodes.

What You’ll Do

• Build and integrate standard cell layout blocks using strict design rules to ensure perfect alignment and seamless cell boundaries.
• Apply systematic layout methodologies to create scalable, uniform, reproducible designs.
• Use industry-standard tools such as Cadence and Calibre for layout creation and verification.
• Maintain and organize layout databases using specialized design management systems.
• Collaborate with a global team to align on design rules, quality expectations, and delivery timelines.
• Troubleshoot design issues, interpret specifications, and produce layout that meets process, electrical, and physical requirements.
• Learn and follow internal methodologies for standard cell architecture and advanced-node processes.
• Track design progress, document updates, and communicate effectively with team leads.

Minimum Qualifications

• Associate’s degree or technical certificate in Computer Science, Mathematics, Electrical Engineering, or related field.
• Strong academic fundamentals in areas such as digital logic, CMOS, programming, or CAD-related coursework.
• Advanced English proficiency.
• Valid U.S. visa (preferred).

Preferred Qualifications

• Bachelor’s degree in Engineering, Computer Science, or related discipline.
• Experience with CAD software for electrical, mechanical, architectural, or PCB design.
• Programming or scripting experience (Python, C, or similar).
• Hands-on experience in board-level design, PCB layout, or electronics lab/test environments.
• Familiarity with semiconductor processes or advanced-node concepts (a plus).