Descripción

We are looking for a highly motivated DDR Bench Test Engineer who is passionate about silicon debug, high‑speed interfaces, and data‑driven optimization of complex mixed‑signal systems. In this role, you will work on cutting-edge LPDDR and DDR technologies while collaborating with world‑class design, systems, and customer engineering teams.

As a DDR Bench Test Engineer, you will develop and execute test methodologies for advanced SoC subsystems—including DRAM, memory controllers, mixed‑signal PHY IP, IO circuits, clocking architectures, and termination networks. You will lead the first‑silicon bring-up, perform detailed electrical characterization, and drive improvements across high‑speed interfaces.

This role involves building automated test flows, analyzing large data sets, debugging silicon issues, and supporting customer-facing investigations in time-critical environments. If you enjoy solving complex technical problems, optimizing performance, and working hands-on with cutting‑edge hardware, this position is a great fit.

Key Responsibilities

• Develop, define, and execute test and characterization methodologies for LPDDR and DDR subsystems.
• Perform electrical characterization of high-speed interfaces, including jitter analysis, eye diagram evaluation, and signal integrity assessments.
• Lead first‑silicon bring-up, debugging, and validation of SoCs manufactured at external foundries.
• Automate test scripts, measurement procedures, and data-processing workflows to accelerate evaluation cycles.
• Analyze large data sets to optimize design parameters and ensure electrical compliance across operating conditions.
• Collaborate closely with IC Design, Systems Engineering, Hardware Applications, and Customer Engineering teams.
• Assist in board‑level signal integrity (SI) and power integrity (PI) debug involving package and PCB design.
• Investigate and resolve customer issues, including RMA/debug in fast‑paced scenarios.
• Document characterization results, debug findings, and methodology updates with clarity and technical rigor.

Preferred Qualifications

• Master’s Degree in Electrical Engineering, Computer Engineering, or related field.
• 3+ years of experience (motivated new graduates encouraged to apply).
• Strong understanding of VLSI technologies, CMOS circuits, mixed‑signal design, and semiconductor device physics.
• Experience with high‑speed test & characterization (eye diagrams, jitter, differential signaling, SI/PI).
• Familiarity with DDR2/3/4/5 and LPDDR2/3/4/5 protocols, timing diagrams, and memory subsystem architectures.
• Hands‑on experience with lab equipment: oscilloscopes, TDRs, VNAs, J‑BERT, etc.
• Knowledge of schematic review, PCB layout best practices, and board‑level debug.
• ASIC device‑level characterization; system‑level understanding is a plus.
• Experience in test automation, scripting, and debugging workflows.
• Strong communication, documentation, and presentation skills.
• Proven problem‑solving skills and ability to work with minimal supervision.
• Collaborative mindset and ability to thrive in a fast‑paced, multi‑disciplinary environment.

Minimum Qualifications

• Fluent English (90% verbal & written).
• Bachelor’s degree in Engineering, Computer Science, or related field.
• 1+ year relevant experience (new graduates welcome).
• Proficiency in Python or C# for test automation.
• Strong initiative, independence, and ability to meet project milestones.
• Excellent written and verbal communication; able to create clear, data‑driven reports.
• Well‑organized, detail‑oriented, and capable of working effectively with local and remote teams.