We are looking for motivated engineers with Static timing analysis skill; good knowledge on timing convergence and corner definition in advanced tech nodes.

If you have expertise in this area and are excited by driving leading edge semiconductor technologies those make differences on this world, this is the opportunity for you.

In this highly visible role, the candidate is expected to coordinate with 100+ engineers, work across multiple design teams in USA and beyond USA, work inside and with outside company/vendor, juggle various tech node issues concurrently.

Experience in various STA tools, timing signoff margin development, Timing sign off Corner development, Full chip timing closure, tape-out, and post-silicon analysis is an excellent skill to have in this position.

As an ASIC Timing analysis engineer, you will be responsible for all aspects of timing including, defining corners, helping construct and/or modify flows, PPA improvement, timing bottleneck analysis and timing closure.

Key Qualifications:

• As an ASIC Timing Engineer, you will play a vital role in Timing analysis targeting the Mobile, Compute, Automotive and IOT markets
• You will be working with physical design on timing closure, CAD teams, IP teams and Design Technology Teams for flow scripts/tools development and validation.
• You will facilitate and drive STA methodology using Primetime, Tempus and best in class timing ECO tools. Knowledge of industry STA tools in depth is key to this role.
• A timing Engineer should be able to understand all kind of intricate timing paths (digital, analog, mixed signal), timing constraints and provide solutions if required. Good understanding of RTL to GDS digital flow is required.
• Familiarity with all areas of timing closure of high-performance, mixed-signal SoCs in sophisticated process technology nodes (40nm to 3 nm).
• Have good Physical Design execution knowledge (Synthesis to timing Sign off). Good knowledge of low-power techniques including clock gating, power gating and multi-voltage designs is required.
• Good programming skills Python, Perl, TCL, Unix shell.  Expertise is required for the development of scripted automation for data processing (related to timing convergence)
• Ability to work & coordinate with large design teams is a MUST
• Timing sign off experience is a plus
• IP design experience is a plus
• Excellent communication skills.
• Excellent multitasking skills.
• Above all, you should be a good team player with ability to remain calm in challenging technical discussions, demanding customers and schedule pressure.