This position involves designing and implementing Low-power, High Performance, area-efficient embedded memory (CPUL1/L2, SRAM, register files, etc.) circuits and architectures.

Responsibilities: 
Develop memory architectures and circuit implementation techniques.
Schematic entry, simulation of major blocks, layout planning, layout supervision and interface with CAD team for full verification and model generation. 

Qualifications in the following areas are required:

• 5+ years of academic or professional experience designing embedded memories for SoC applications.
• Strong Technical expertise in CPUL1/L2, Compiler SRAM/Register File architectures and advanced custom circuit implementations.
• Full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, timing and model generation.
• Physical implementation (layout) and layout supervision.
• Advanced technology nodes.

Preferred qualifications in the following areas are a plus:

• Experience with tight pitch-matched memory layout designs.
• Understanding of physical implementation impact on circuit performance.
• Familiarity with variation-aware design in nano-meter technology nodes.
• Experience with low power design features and flows.

Education Requirements 
Bachelors Degree in Electrical, electronics engineering or related,

Master's, Electrical Engineering, PhD, Electrical Engineering.