Job Overview

In this highly cross functional role, you will be part of the Global Design Enablement team responsible for the physical verification aspects of PDK development. You will conceptualize, develop, maintain, and improve the Physical Verification flows. The role requires you to work on flow and rule deck development for various technology nodes utilizing the state-of-the-art tools. You will be collaborating with the Custom Digital/Analog/Mixed Signal/RF, Physical design (PD) and Chip integration teams to understand their requirements and challenges, enabling flows to meet their needs. This role requires a thorough understanding of Design Rule Checks (DRC), Layout Versus Schematic (LVS) and Layout and Programmable ERC, implementing the rules from scratch and/or modifying the existing ones.

Minimum Qualification

Minimum 2 years of experience in a hands-on PDK role.

• Expertise in Calibre/ICV/Pegasus runset coding for DRC/LVS/ERC/PERC/MPT/ESD/Latch-up/Antenna, etc.
• Experience with developing and customization of the StarRC/Calibre-xACT/QRC parasitic extraction flows.
• As a member of the Physical Verification CAD team, you will maintain and improve all aspects of physical verification flow and methodology.
• Code custom checks such as Layout/Programmable ERCs, addition of custom devices in LVS, implementation of custom design rules (DRCs), etc., to meet design team requirements.
• You will need to have a deep understanding of design rule checks (DRC) and layout versus schematic (LVS) runsets, writing from scratch and/or modifying existing ones.
• Proficiency in integration and tech setup of Calibre LVS with StarRC/QRC and other extraction tools.
• Utilizing your hands-on skills to revamp/rewrite and streamline the PEX flow.
• Understanding of Digital/Custom/Analog requirements for various post layout electrical flows.
• Develop custom extraction solutions for transistor level for design team requirements.
• Hands-on experience with Field solvers and RC reduction tools.
• Support design teams with solving their PEX challenges.
• Support the design teams with solving their PV challenges to facilitate the IP release and chip tapeouts.
• Collaborate with tool vendors and foundries for tools and flow improvements.
• Knowledge of deep sub-micron FINFET, Planar, SOI and PMIC process technologies and mask layout design.
• Proficiency in one or more of the programming/scripting languages – SKILL, Python, Unix, Perl and TCL.
• Good communication skills and ability to work collaboratively in a team environment.

Educational Requirements

Required: Bachelor's, Electrical Engineering (with Master’s preferred).